This invention relates to semiconductor process equipment and more particularly, to Chemical Vapor Deposition apparatus for performing a plurality of in-situ processes for forming all or portions of an electronic device.
Present Chemical Vapor Deposition Equipment consists of a single or multiple chambers, gas inlets, gas outlets, vacuum pumps and transfer load-lock systems for inserting, for example, semiconductor wafers into the chamber. Prior art examples of Chemical Vapor Deposition Equipment is described in U.S. Pat. No. 5,298,452 by B. S. Meyerson which issued on Mar. 29, 1994 which shows an Ultra High Vacuum Chemical Vapor Deposition (UHV-CVD) reactor with a vacuum loading apparatus.
An example of a cluster CVD system which is for single wafer processing with preheating and uniform temperature control is described in U.S. Pat. No. 5,259,881 by Edwards et al. which issued on Nov. 9, 1993.
In the growth of Si structures or Si/SiGe heterostructures via UHV-CVD processing, a critical step and requirement before loading wafers into the UHV-CVD equipment is to perform a dip of each Si containing wafer into HF acid to remove the native oxide from the wafer surface and to passivate the Si bonds at the surface with hydrogen. Si containing wafers after being dipped in HF acid are loaded into a vacuum loading apparatus of a CVD reactor and then inserted into the CVD reactor. This particular ex-situ HF cleaning procedure without a water rinse is a hazardous practice to be performed manually under a chemical hood and moreover, for patterned wafers, often there is residual HF liquid left on the wafer surface which would require additional N2 blowing of the residual HF off the wafer. Blowing residual liquid HF is an extremely hazardous manual process. Presently, this HF-dip is not an industry acceptable process and weakens the acceptance of the UHV-CVD processing technique for doing low temperature epitaxy in the semiconductor manufacturing industry.
Another key issue related to making high performance Si and/or Si/SiGe Metal Oxide Silicon (MOS) field effect transistor (FET) structures and/or Complementary Metal Oxide Silicon (CMOS) is the requirement for a very high quality gate dielectric and a gate electrode stack as described in U.S. Pat. No. 5,534,713 by K. Ismail et al. which issued Jul. 9, 1996. This patent describes a gate dielectric of an ultra-thin SiO2 layer with a thickness from 1 nm to 5 nm. The gate electrode is a heavily doped polysilicon structure.
In accordance with the present invention, an apparatus is described for forming the semiconductor portion of CMOS, MODFET""s, MOSFET""s, HEMT""s etc. along with any desired gate structure such as an ultra thin gate oxide together with a heavily doped polysilicon gate electrode layer to be subsequently patterned comprising an Ultra High Vacuum-Chemical Vapor Deposition System (UHV-CVD), a Low Pressure CVD (LP-CVD), and an UHV transfer system for loading wafers from the external ambient and for transferring wafers from UHV-CVD to LP-CVD and vice versa under UHV pressures. A separate load-lock could be provided for transfer of wafers from the external ambient to an UHV transfer system where the UHV transfer system would remain at vacuum pressures.
The invention further provides an apparatus for performing a plurality of processes comprising a first UHV-CVD system, a second CVD system positioned above the first UHV-CVD system, a transfer system for transferring semiconductor wafers between the first and second systems under UHV pressure, wherein the UHV transfer system includes an elevator mechanism for raising and lowering the semiconductor wafers from one CVD system or reactor to the other.
The invention further provides an apparatus for performing a plurality of processes comprising a first UHV-CVD system, a second CVD system positioned horizontally beside the first UHV-CVD system, a transfer system for transferring semiconductor wafers between the first and second systems under UHV pressure, wherein the transfer system includes a mechanism for moving the semiconductor wafers from one CVD system or reactor to the other.
The invention further provides a method for passivating a silicon containing surface on a substrate comprising the steps of placing the substrate in a reactor, prebaking the substrate surface in hydrogen, growing a silicon containing layer with a first gas, switching the first gas to a second gas such as SiH4 or Si2H6, and reducing the growth temperature to below 400xc2x0 C. The surface passivation with hydrogen is hydrophobic and serves to prevent any surface oxidation to occur.
The invention further provides a method for continuous epitaxial growth on a semiconductor substrate in a reactor comprising the steps of growing an epitaxial layer on the semiconductor substrate under first growth conditions, interrupting the growth of the epitaxial layer, passivating the surface of the substrate with hydrogen such as by flowing SiH4 or Si2H6 while lowering the substrate surface temperature below 400xc2x0 C.
The invention further provides changing the first growth conditions to second growth conditions in the reactor and restarting continuous growth on the surface of the epitaxial layer under the second growth conditions such as by raising the temperature of the substrate above 400xc2x0 C.
The invention further provides a method for continuous epitaxial growth on a semiconductor substrate in a plurality of reactors comprising the steps of growing an epitaxial layer in a first reactor, interrupting the growth of the epitaxial layer, passivating the surface of the substrate such as by lowering the temperature of the substrate below 400xc2x0 C. with hydrogen such as by flowing SiH4 or Si2H6, transferring the substrate to a second reactor while maintaining a controlled gaseous environment and pressure between reactors and restarting continuous growth on the surface of the epitaxial layer in the second reactor such as by flowing a silicon containing gas and raising the temperature of the substrate above 400xc2x0 C. The controlled gaseous environment herein is an environment that may include hydrogen and excluding contaminants such as O2, CO2, CO, H2O, CH4, and other hydrocarbons and gases such as mentioned in U.S. Pat. No. 5,298,452 as contaminants which is incorporated herein by reference. The partial pressure of all contaminants are maintained at pressures below 108 Torr.
The invention further provides a method for forming a silicon/silicon oxide interface with low interface traps comprising the steps of growing a silicon containing layer on a substrate with a first gas in a first CVD reactor, switching the first gas to a second gas such as SiH4 or Si2H6 to passivate the surface of the substrate with hydrogen terminated Si bonds, reducing the temperature from the growth temperature to below 400xc2x0 C., transferring the substrate to a second CVD reactor while maintaining a controlled gaseous environment and pressure between CVD reactors and growing a silicon oxide layer on the passivated surface.
The invention further provides a method for fabricating silicon containing epitaxial layers comprising the steps of placing a semiconductor substrate into a first CVD reactor, removing any native oxide from the surface of the semiconductor substrate by baking in the range from 850xc2x0 C. to 900xc2x0 C. for about 30 minutes in the first CVD reactor with hydrogen gas flowing in the first CVD reactor, forming a medium/high temperature silicon containing epitaxy layer on the surface of the semiconductor substrate in the range from 600xc2x0 C. to 900xc2x0 C. in the first CVD reactor, flowing a hydrogen containing gas in the first CVD reactor, reducing the growth temperature in the range from 400xc2x0 C. to 350xc2x0 C. whereby the surface of the semiconductor substrate is hydrogen terminated, transferring the semiconductor substrate to a second UHV-CVD reactor under a controlled gaseous environment, and forming epitaxial layers on the semiconductor substrate suitable for the channel of a FET. Next, the semiconductor substrate may be transferred to a third CVD reactor under a controlled gaseous environment, forming a gate oxide on the upper surface of the semiconductor substrate, transferring the semiconductor substrate to a fourth CVD reactor under a controlled gaseous environment, and forming a heavily doped n or p type polysilicon gate electrode layer over the gate oxide. The n or p type doping may be in the range from 1xc3x971020 to 1xc3x971021 atoms/cm3. The first and third CVD reactor may be the same one. The second and fourth CVD reactor may be the same one.
The invention further provides a method for forming two successive processes comprising the steps of placing a semiconductor substrate into a CVD reactor, performing a first process, passivating the surface of the semiconductor substrate, removing the semiconductor substrate from the CVD reactor, purging the CVD reactor with hydrogen, reintroducing the semiconductor substrate into the CVD reactor while maintaining the semiconductor substrate below 400xc2x0 C., and performing a second process. The first and second processes may including growing Si containing layers with different compositions, dopants, growth conditions etc.